Clock signals are used throughout computer systems to facilitate the correct timing of events within the computer system. For example, if a sequence of events must occur in a particular order or must occur simultaneously, then clock signals may be used to ensure that the events occur at the correct timings.
A clock signal having a constant period (or “time period”) is useful in providing an accurate measure of time in a computer system. The time interval between consecutive rising edges is constant for a clock signal with a constant (or “uniform”) period. In the frequency domain, a clock signal having a constant period will have a narrow peak of high-amplitude at the fundamental frequency corresponding to the inverse of the period of the clock signal. The clock signal will also have a series of other narrow peaks of lower amplitude than the peak of the fundamental frequency, which correspond to harmonics of the clock signal. When the clock signal has a constant period, the energy of the harmonics is contained within narrow bandwidths and as such the harmonics have a relatively high Power Spectral Density (PSD) (which has units of Power/Hz).
The frequency of the clock signal can be set such that it will not interfere in particular frequency bands which may be reserved for purposes other than for clock signals. However, the harmonics of the clock signal may fall into a reserved frequency band and cause interference within the reserved frequency band. For example, the clock signal may be used within a device which communicates using the Global System for Mobile Communications (GSM) standard. According to the GSM standard the energy of received signals within particular frequency channels (which are typically of the order of 100 kHz in bandwidth) is measured in order to correctly receive and interpret the received signals. The signals are received at the device over a wireless channel and may have a low signal strength, making them very susceptible to interference from clock harmonics. If there is too much interference from such a harmonic in a particular radio channel, then the sensitivity of the receiver to a radio signal could be degraded unacceptably.
As is known in the art, a phase locked loop (PLL) may be used to generate a clock signal within a device. PLLs use a voltage controlled oscillator (VCO) and a feedback mechanism to set the frequency of the generated clock signal. Spread spectrum frequency dithering (SSFD) is a method by which the voltage supplied to a VCO within a PLL can be “dithered”, that is, varied slightly around the usual voltage supplied to the VCO. In this way the clock signal generated by the PLL will have a period which varies slightly (or “dithers”) around the usual clock period. Whilst this dithering can reduce the accuracy of the clock signal for use in correctly timing events within a computer system, the dithering will spread out the peaks of the clock signal in the frequency domain. This means that the peak strengths of the fundamental frequency and of the harmonics of the clock signal will be reduced and the peaks will be spread over a larger frequency bandwidth. By spreading the peaks over a bandwidth which is larger than the bandwidth of the receive channels in a GSM device, the PSD of the harmonics of the clock signal within each receive band is reduced, and therefore the effect of the interference resulting from the harmonics of the clock signal can be reduced.